1. Field
Embodiments of the present invention apply to the field of integrated circuit clock generation and supply and, in particular, to generating multiple aligned clocks from a single reference clock.
2. Background
Microprocessors and other controllers require a clock to time the operation of internal circuits and processes. Some processor and controllers have multiple clocks to support a variety of different internal clock domains. The different clock domains can include I/O (Input/Output), data, address, strobe, processing, memory interface, controller interface etc. In many microprocessors, each clock domain has its own clock source, or at least its own PLL (Phase Locked Loop) to generate the internal clock frequency necessary to support that clock domain. In order to support communication across clock domains, the multiple clock domain signals are often aligned with respect to each other.
A bypass clock function is available on a wide range of test platforms. The bypass clock function allows the processor's or controller's clocks and PLLs to be circumvented so that an external tester can precisely control the circuits' clock speeds. The bypass clock speeds may be much lower than the lowest speeds supported by internal PLLs so that internal clocking and synchronization cannot be used. In functional tests for a microprocessor, a bypass clock may be used that operates at 50-100 MHz instead of the circuits' typical 2-3 GHz. Some functional testers may even pulse the bypass clock in individual steps to allow functions at each clock cycle to be evaluated. Bypass clocks may also be used for burn-in testing of microprocessors and controllers. For example, instead of running the circuits at high speed, the circuits may be cycled for burn-in testing at low speed and high temperatures.
The multiple clock domains and the desire for alignment cause difficulties especially in testing. Structural testers and other debug platforms often do not have enough clock pins to support all of the different PLLs and clocks in a bypass or test mode. In addition, the internal clock domains may require alignment with each other and with the tester's internal bus clock in order for tests to successfully be performed. The internal alignment cannot be performed by internal PLLs when the clock speeds are too low for the internal PLLs. The alignment of the internal clock domains with the tester's internal clock bus is typically done manually. With some testers, it is done by the external tester in an automated iteration process that requires many cycles to find sufficient alignment. This can be expensive and time-consuming.